 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY2300 Phase-Aligned Clock Multiplier Features * * * * * * * * * * 4-multiplier configuration Single phase-locked loop architecture Phase Alignment Low jitter, high accuracy outputs Output enable pin 3.3V operation 5V Tolerant input Internal loop filter 8-pin 150-mil SOIC package Commercial and Industrial Temperature available Benefits * 1/2x, 1x, 1x, 2x Ref * 10 MHz to 166.67 MHz operating range (reference input from 20 MHz to 83.33 MHz) * All outputs will have a consistent phase relationship with each other and the reference input * Meets critical timing requirements * Enables design flexibility and lower power consumption * Supports industry standard design platforms * Allows flexibility on Reference input * Alleviates the need for external components * Industry standard packaging saves on board space * Suitable for wide spectrum of applications Selector Guide Part Number CY2300SC CY2300SI Outputs 4 4 Input Frequency Range 20 MHz-83.33 MHz 20 MHz-83.33 MHz Output Frequency Range 10 MHz-166.67 MHz 10 MHz-166.6 7MHz Specifics Commercial Temperature Industrial Temperature Block Diagram FBK Pin Configuration 8-pin SOIC Top View 1/2xREF REFIN /2 PLL Divider Logic REF REF 1/2xREF GND REFIN REF 1 2 3 4 8 7 6 5 OE VDD 2xREF REF 2xREF OE Cypress Semiconductor Corporation Document #: 38-07252 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised July 26, 2004 CY2300 Pin Definitions Pin 1 2 3 4 5 6 7 8 GND REFIN REF REF 2xREF VDD OE Signal[1] 1/2xREF Clock output, 1/2x Reference Ground Input Reference frequency, 5V tolerant input Clock output Reference Clock output Reference Clock output, 2x Reference 3.3V Supply Output Enable (weak pull-up) The CY2300 is available in commercial and industrial temperature ranges. Description Functional Description The CY2300 is a 4-output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins. The part has an on-chip PLL which locks to an input clock presented on the REFIN pin. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2300 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. Maximum Ratings Supply Voltage to Ground Potential ...............-0.5V to +7.0V DC Input Voltage (Except Ref) .............. -0.5V to VDD + 0.5V DC Input Voltage REF ........................................... -0.5 to 7V Storage Temperature ................................. -65C to +150C Junction Temperature.................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions for CY2300SC Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance,133.33 MHz < Fout < 166.67 MHz Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.0 0 Max. 3.6 70 18 12 7 50 Unit V C pF pF pF ms Electrical Characteristics for CY2300SC Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage Supply Current [2] Description Min. 2.0 Max. 0.8 Unit V V A A V V mA mA mA VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 66 MHz Unloaded outputs, REFIN = 33 MHz Unloaded outputs, REFIN = 20 MHz 2.4 100 50 0.4 45 32 18 Notes: 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Document #: 38-07252 Rev. *B Page 2 of 7 CY2300 Switching Characteristics for CY2300SC Commercial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK [3] Test Conditions 18-pF load 12-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Min. 10 40 Typ. Max. 133.33 166.67 Unit MHz MHz % ns ns ps ps ps ps ms = t2 / t1 50 60 1.20 1.20 200 200 400 175 1.0 Rise Time[3] Fall Time[3] Output to Output Skew on rising edges[3] Delay, REFIN Rising Edge to Out- Measured at VDD/2 from REFIN to any put Rising Edge[3] output Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 on the 1/2xREF pin of devices (pin 1) Measured at Fout=133.33 MHz, loaded outputs, 18-pF load Stable power supply, valid clocks presented on REFIN Operating Conditions for CY2300SI Industrial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance,133.33 MHz < Fout < 166.67MHz Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.0 -40 Max. 3.6 85 15 10 7 50 Unit V C pF pF pF ms Electrical Characteristics for CY2300SI Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage[2] Supply Current VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 66 MHz Unloaded outputs, REFIN = 33 MHz Unloaded outputs, REFIN = 20 MHz Note: 3. All parameters are specified with equally loaded outputs. Test Conditions Min. 2.0 Max. 0.8 100 50 0.4 Unit V V A A V V mA mA mA 2.4 48 35 20 Document #: 38-07252 Rev. *B Page 3 of 7 CY2300 Switching Characteristics for CY2300SI Industrial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK Rise Time Fall Time [3] Test Conditions 15-pF load 10-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Min. 10 40 Typ. Max. 133.33 166.67 Unit MHz MHz % ns ns ps ps ps ps ms = t2 / t1 50 60 1.20 1.20 200 200 400 175 1.0 [3] [3] Output to Output Skew on ris- All outputs equally loaded ing edges[3] Measured at VDD/2 Delay, REFIN Rising Edge to Output Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 from REFIN to any output Measured at VDD/2 on the 1/2xREF pin of devices (pin 1) Measured at Fout=133.33 MHz, loaded outputs, 15-pF load Stable power supply, valid clocks presented on REFIN Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 All Outputs Rise/Fall Time 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V OUTPUT Output-Output Skew OUTPUT VDD/2 OUTPUT t5 VDD/2 Document #: 38-07252 Rev. *B Page 4 of 7 CY2300 Switching Waveforms Input-Output Propagation Delay REFIN VDD/2 OUTPUT t6 VDD/2 Device-Device Skew 1/2xREF, Device1 VDD/2 1/2xREF, Device2 t7 VDD/2 Test Circuits Test Circuit # 1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Document #: 38-07252 Rev. *B Page 5 of 7 CY2300 Ordering Information Ordering Code CY2300SC CY2300SC CY2300SI CY2300SI Lead Free CY2300SXC CY2300SXCT CY2300SXI CY2300SXIT 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Commercial Commercial Industrial Industrial Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Operating Range Commercial Commercial Industrial Industrial Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07252 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2300 Document Title: CY2300 Phase-Aligned Clock Multiplier Document Number: 38-07252 REV. ** *A *B ECN NO. 110517 121854 246829 Issue Date 01/07/02 12/14/02 See ECN Orig. of Change SZV RBI RGL Description of Change Change from Spec number: 38-01039 to 38-07252 Power up requirements added to Operating Conditions Information Added Lead Free Devices Document #: 38-07252 Rev. *B Page 7 of 7 |
Price & Availability of CY2300
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |